Power consumption is a major consideration in integrated circuit (IC) design. In circuits containing millions of transistors there are many control signals, some of which are used by the designers of the circuits to reduce the power consumption of sub-circuits or even the entire IC. Certain control signals are known in advance of the design and as such are used to enable or disable the circuit or portions thereof from clocking while idle and thereby power consumption is reduced. Such control signals are generally referred to as critical signals. That is, a critical signal is a signal which controls the activity of this module. When the signal toggles, the module starts its processing and its activity increases.
For instance, critical signals can be found when there is a control unit that sends start and end signals to a processing element. This can also be the case when a first-in first-out (FIFO) circuit is used for synchronization. There will be signals from the FIFO circuit controlling one or more modules to read data from it. These signals are critical as they will trigger activity in the module. While a designer of a circuit may take precautions in an attempt to prevent missing such critical signal, this may be a daunting task when circuits containing millions of transistors are involved and each designer concentrating on the design of only a much smaller portion of the overall IC. While certain signal such as clocks or enable signals may be identified by the designer as critical signals, and handled as such, it is easy to miss interactions between modules and sub-circuits and thereby lose opportunities for significant power reductions.
It would therefore be advantageous to provide a solution that identifies critical signals that can provide power savings if handled properly. It would be advantageous if the solution can provide indications for savings that do not require the finer granularity power savings provided by techniques involving stability condition (STC) and observability don't-care (ODC) analysis.